1. Field of the Invention
The present disclosure generally relates to the field of semiconductor techniques, and more specifically, it relates to chip-to-wafer bonding technology.
2. Description of the Related Art
With the development of semiconductor technologies, three-dimensional (3D) integration technology has attracted more attention. Compared with conventional two-dimensional integration technology, 3D integration technology can enhance signal processing speed and lower power consumption. 3D integration technology introduces wafer-to-wafer bonding, chip-to-wafer bonding and chip-to-chip bonding. Among these, chip-to-wafer bonding uses known good dies (KGDs) for integration and thus has a high yield.
Conventional chip-to-wafer 3D integration uses pick-and-place chip assembly, as shown in FIG. 1. In FIG. 1, reference numeral 110 denotes a single chip pick-up tool, 120 denotes a chip tray, 130 denotes a wafer and 140 denotes a chip. This pick-and-place chip assembly technique has low alignment accuracy therefore a serious trade-off problem between assembly throughput and alignment accuracy.
To overcome this problem, a method for chip-to-wafer 3D integration using self-assembly technique has been proposed (see: Three-Dimensional Integration Technology Using Self-Assembly Technique and Super-Chip Integration, Koyanagi, Mitsumasa; Fukushima, Takafumi; Tanaka, Tetsu; International Interconnect Technology Conference, 2008, Page 10-12). This method employs a particular liquid for helping the alignment and bonding of chip and wafer during a chip-to-wafer bonding process. FIG. 2 shows a process of placing four chips onto a wafer using this self-assembly technique. As shown in FIG. 2, on the surface of wafer 210, bonding regions 220 on which chips are to be placed are subject to surface hydrophilic treatment and regions 230 surrounding the bonding regions 220 are subject to hydrophobic treatment. Then, liquid 240 is dropped onto the hydrophilic bonding regions on the wafer's surface. After that, chips 250 with hydrophilic backsides are placed onto the bonding regions of the wafer. When placing the chips, the chips may be just roughly aligned with the corresponding bonding regions of the wafer. Subsequently, the chips 250 are precisely aligned with the bonding regions 220 under the action of liquid surface tension. This method has relatively high alignment accuracy.